mirror of https://github.com/zachjs/sv2v.git
50 lines
1.1 KiB
Systemverilog
50 lines
1.1 KiB
Systemverilog
`define TEST(value) \
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logic [63:0] val_``value = 'value; \
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initial $display(`"'value -> %b (%0d) %b (%0d)", \
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val_``value, $bits(val_``value), \
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'value, $bits('value) \
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);
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module top;
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`TEST(1);
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`TEST(0);
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`TEST(x);
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`TEST(z);
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logic flag;
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logic [31:0] i;
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logic [31:0] a;
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logic [31:0] b;
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logic [31:0] c;
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logic [63:0] j;
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logic [63:0] d;
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logic [63:0] e;
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initial begin
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i = 42;
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j = 42;
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flag = 1;
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a = (flag ? '1 : i);
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b = (flag ? 'x : i);
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c = (flag ? '1 : '0);
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d = (flag ? '1 : j);
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e = (flag ? 'x : j);
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$display("%b", a);
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$display("%b", b);
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$display("%b", c);
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$display("%b", d);
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$display("%b", e);
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end
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initial begin
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$display("%b", {'1, 'x, 'z, '0});
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$display("%b", {2 {'1, 'x, 'z, '0}});
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end
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initial begin
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$display($bits('1));
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$display($bits(flag ? '1 : 'x));
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$display($bits(type('1)));
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$display($bits(type(flag ? '1 : 'x)));
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end
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endmodule
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