mirror of https://github.com/zachjs/sv2v.git
34 lines
852 B
Verilog
34 lines
852 B
Verilog
module Suite;
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parameter WIDTH = 1;
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`include "inside_exhaust.vh"
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function [0:0] test_weq;
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input [WIDTH-1:0] x, y;
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integer idx;
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begin
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test_weq = 1'b1;
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for (idx = 0; idx < WIDTH; idx = idx + 1) begin
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if (y[idx] === 1'bx || y[idx] === 1'bz)
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;
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else if (x[idx] === 1'bx || x[idx] === 1'bz)
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test_weq = 1'bx;
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else if (y[idx] !== x[idx]) begin
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test_weq = 1'b0;
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idx = WIDTH;
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end
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end
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end
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endfunction
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function [0:0] test_inside;
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input [WIDTH-1:0] x, y, z;
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test_inside = |{test_weq(x, y), test_weq(x, z)};
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endfunction
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endmodule
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module top;
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Suite #(1) a();
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Suite #(2) b();
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Suite #(3) c();
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endmodule
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