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14 lines
262 B
Verilog
14 lines
262 B
Verilog
module top;
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reg [3:0] arr;
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initial begin : block_name
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integer i;
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for (i = 0; i < 4; i++)
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arr[i] = i;
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end
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initial $display(arr);
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parameter foo = 1;
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localparam bar = 1;
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initial $display(foo, bar);
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endmodule
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