mirror of
https://github.com/zachjs/sv2v.git
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- module instances with modport bindings are now inlined - support for modports in generate loops - support for generic interfaces - implied modport instance propagation - add error message for interface instances missing port list
28 lines
576 B
Verilog
28 lines
576 B
Verilog
module M(data);
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parameter A = 1;
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parameter WIDTH = 32;
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parameter B = 2;
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localparam OFFSET = 1;
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input wire [WIDTH-OFFSET:0] data;
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initial begin
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$display("A %b", A);
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$display("I.P %b", data);
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$display("B %b", B);
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end
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endmodule
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module top;
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generate
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begin : x
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wire [31:0] data = 0;
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end
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begin : y
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wire [9:0] data = 0;
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end
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endgenerate
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M #(.WIDTH(32)) a(x.data);
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M #(.WIDTH(10)) b(y.data);
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M #(3, 32, 4) c(x.data);
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M #(5, 10, 6) d(y.data);
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endmodule
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