mirror of
https://github.com/zachjs/sv2v.git
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Zachary Snow
67466eaa60
- module instances with modport bindings are now inlined - support for modports in generate loops - support for generic interfaces - implied modport instance propagation - add error message for interface instances missing port list
24 lines
516 B
Verilog
24 lines
516 B
Verilog
module top;
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wire x = 1;
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generate
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begin : f
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wire x;
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begin : a
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wire x;
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initial begin
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$display("bar got %b", x);
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end
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end
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assign a.x = x;
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begin : b
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wire x;
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initial begin
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$display("bar got %b", x);
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end
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end
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assign b.x = ~x;
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end
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assign f.x = x;
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endgenerate
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endmodule
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