mirror of
https://github.com/zachjs/sv2v.git
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Zachary Snow
8eb3a251f7
- full import and export support - simplify AST representation of import and export - allow package-scoped identifiers invoked as subroutines - use scoped name resolution for identifiers in packages - merge package item nesting conversion into package conversion - fix handling of colliding enum items in separate modules - fix visiting enum item exprs in types
15 lines
320 B
Verilog
15 lines
320 B
Verilog
module ExampleA;
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localparam [0:0] A = 1;
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localparam [0:0] B = 0;
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reg x = A;
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initial $display("ExampleA: x=%b, A=%b, B=%b", x, A, B);
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endmodule
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module ExampleB;
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localparam [0:0] A = 0;
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localparam [0:0] B = 1;
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reg x = A;
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initial $display("ExampleB: x=%b, A=%b, B=%b", x, A, B);
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endmodule
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