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Zachary Snow
2a2d819baa
- assertions, gen case, and inout - simplify block codegen - remove blank lines in tasks with no inputs
9 lines
173 B
Verilog
9 lines
173 B
Verilog
module Module(input clock, input clear, input data);
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wire x, y;
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assign y = data;
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assign x = y;
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task hello;
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$display("Hello!");
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endtask
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endmodule
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