mirror of https://github.com/zachjs/sv2v.git
27 lines
457 B
Verilog
27 lines
457 B
Verilog
`default_nettype none
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// typedef struct packed {
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// logic [1:0] last;
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// logic [1:0] first;
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// } MyStruct_t;
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module Example(
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input wire [1:0] a, b,
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output wire [3:0] result
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);
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reg [3:0] s;
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assign result = s;
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// Convert to always @* block
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// It might be easier to go directly to always @*
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wire [1:0] _s_3_2;
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assign _s_3_2[1:0] = a;
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always @* s[3:2] = _s_3_2;
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always @* begin
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s[1:0] = b;
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end
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endmodule |