mirror of https://github.com/zachjs/sv2v.git
24 lines
510 B
Verilog
24 lines
510 B
Verilog
`default_nettype none
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module top;
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reg [7:0] doubleNibble;
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wire [3:0] sum;
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Device dut(
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.doubleNibble(doubleNibble),
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.sum(sum)
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);
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reg [8:0] i; // Note that i is 1 bit wider than doubleNibble
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initial begin
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$monitor($time, " %h + %h = %h", doubleNibble[7:4], doubleNibble[3:0], sum);
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doubleNibble = 8'h00;
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for(i = 0; i <= 8'hff; i = i + 8'h1) begin
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#10 doubleNibble = i; // This drops upper order bits
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end
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end
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endmodule
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