mirror of https://github.com/zachjs/sv2v.git
42 lines
886 B
Verilog
42 lines
886 B
Verilog
`default_nettype none
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module top;
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reg [7:0] dataIn;
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wire [31:0] dataOut;
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reg clock, clear;
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Device dut(
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.dataIn(dataIn),
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.dataOut(dataOut),
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.clock(clock),
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.clear(clear)
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);
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// Just some random test bench code to make sure it works as expected
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initial begin
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clock = 1;
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forever #5 clock = ~clock;
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end
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initial begin
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$monitor($time," dataIn: %h dataOut: %h shift: %b", dataIn, dataOut, dut.consumer.local_shift);
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clear <= 1'b1;
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dataIn <= 8'h0;
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repeat(5) @(posedge clock);
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clear <= 1'b0;
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@(posedge clock);
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dataIn <= 8'h44;
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@(posedge clock);
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dataIn <= 8'h77;
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@(posedge clock);
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dataIn <= 8'h11;
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@(posedge clock);
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dataIn <= 8'h0;
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repeat(5) @(posedge clock);
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$finish;
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end
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endmodule
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