mirror of https://github.com/zachjs/sv2v.git
50 lines
921 B
Verilog
50 lines
921 B
Verilog
`default_nettype none
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module Device(
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input wire [31:0] data,
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output wire parity
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);
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wire [3:0] partParity;
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Helper bottom(data[7:0], partParity[0]);
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Helper bottomMid(.parity(partParity[1]), .data(data[15:8]));
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Wrapper1 topMid(.data(data[23:16]), .parity(partParity[2]));
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Wrapper2 top(.data(data[31:24]), .parity1(partParity[3]));
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assign parity = ^partParity;
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endmodule
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module Helper(
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input wire [7:0] data,
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output wire parity
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);
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// This is a bit-wise reduction operator
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assign parity = ^data;
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endmodule
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module Wrapper1(
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input wire [7:0] data,
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output wire parity
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);
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// Expand .* from SystemVerilog
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Helper doTheRightThingMode(.data(data), .parity(parity));
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endmodule
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module Wrapper2(
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input wire [7:0] data,
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output wire parity1
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);
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// Expand .data from SystemVerilog
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Helper compilerSaveMe(.data(data), .parity(parity1));
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endmodule |