mirror of https://github.com/zachjs/sv2v.git
60 lines
1.6 KiB
Systemverilog
60 lines
1.6 KiB
Systemverilog
`default_nettype none
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module Device(
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input logic [31:0] data,
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output logic parity
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);
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logic [3:0] partParity;
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// This is passing a bit-slice as the input to the module assuming that all
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// of the ports are connected in order.
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Helper bottom(data[7:0], partParity[0]);
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// This is the most common syntax explicitly binding the names of the
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// connections to avoid errors where the order of the port definitions change.
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Helper bottomMid(.parity(partParity[1]), .data(data[15:8]));
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Wrapper1 topMid(.data(data[23:16]), .parity(partParity[2]));
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Wrapper2 top(.data(data[31:24]), .parity1(partParity[3]));
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assign parity = ^partParity;
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endmodule
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module Helper(
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input logic [7:0] data,
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output logic parity
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);
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// This is a bit-wise reduction operator
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assign parity = ^data;
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endmodule
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module Wrapper1(
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input logic [7:0] data,
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output logic parity
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);
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// This is SystemVerilog shorthand to make it easy to write trivial systems.
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// For the most part the wire names don't line up nicely so this doesn't
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// work. The compiler replaces ".*" with ".data(data), .parity(parity)" and
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// typically checks that the port widths are consistent.
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Helper doTheRightThingMode(.*);
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endmodule
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module Wrapper2(
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input logic [7:0] data,
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output logic parity1
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);
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// This is a SystemVerilog shorthand similar to .* but actually usable in
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// real projects since it only applies to a specific port. The compiler
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// replaces the ".data" as ".data(data)" and typically checks that the port
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// widths are consistent.
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Helper compilerSaveMe(.data, .parity(parity1));
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endmodule |