mirror of https://github.com/zachjs/sv2v.git
45 lines
814 B
Verilog
45 lines
814 B
Verilog
`default_nettype none
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module top;
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reg clock, clear;
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reg a;
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wire x;
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FSM dut(
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.clock(clock),
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.clear(clear),
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.a(a),
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.x(x)
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);
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initial begin
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clock = 1;
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forever #5 clock = ~clock;
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end
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initial begin
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$monitor($time, " a: %b x: %b state: %h", a, x, dut.currentState);
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clear = 1'b1;
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a = 1'b0;
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repeat(3) @(posedge clock);
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clear = 1'b0;
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a = 1'b1;
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repeat(5) @(posedge clock);
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a = 1'b0;
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repeat(5) @(posedge clock);
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a = 1'b1;
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@(posedge clock);
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a = 1'b0;
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@(posedge clock);
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a = 1'b1;
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@(posedge clock);
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a = 1'b1;
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@(posedge clock);
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a = 1'b0;
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@(posedge clock);
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$finish;
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end
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endmodule
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