mirror of https://github.com/zachjs/sv2v.git
28 lines
701 B
Systemverilog
28 lines
701 B
Systemverilog
`default_nettype none
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// Technically the value assignment could be anything, but most tools default to a 32-bit logic assigning MODE_A = 0 and MODE_B = 1
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typedef enum {MODE_A, MODE_B} Mode_t;
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typedef enum logic [1:0] {READ=2'd1, WRITE=2'd2, NONE=2'd0} Operation_t;
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module Example(
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input logic rawMode,
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output logic [1:0] rawOperation
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);
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Mode_t mode;
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Operation_t operation;
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// cast into a strongly typed variant
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assign mode = Mode_t'(rawMode);
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assign rawOperation = operation;
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always_comb begin
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case(mode)
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MODE_A: operation = READ;
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MODE_B: operation = WRITE;
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default: operation = NONE;
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endcase
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end
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endmodule |