mirror of https://github.com/zachjs/sv2v.git
41 lines
777 B
Verilog
41 lines
777 B
Verilog
`default_nettype none
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module Device(
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input wire clock, clear,
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output wire [3:0] data
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);
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SharedMemory memory(
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.clock1(clock),
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.clock2(clock),
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.clear(clear), // Verilog doesn't support inferred ports
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.data1(data[1:0]),
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.data2(data[3:2])
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);
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endmodule
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module SharedMemory(
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input wire clock1, clock2, clear,
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output reg [1:0] data1, data2
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);
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reg [3:0] memory;
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// Just a dumb example to generate interesting values
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always @(posedge clock1) begin
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if(clear)
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memory <= 4'b0;
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else
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memory <= {~memory[2:0], 1'b0};
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end
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always @(posedge clock1)
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data1 <= memory[1:0];
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always @(posedge clock2) begin
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data2 <= memory[3:2];
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end
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endmodule |