mirror of https://github.com/zachjs/sv2v.git
58 lines
1.1 KiB
Systemverilog
58 lines
1.1 KiB
Systemverilog
interface CacheSetInterface(
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input logic [7:0] request,
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output logic [7:0] response
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);
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modport CacheSet(
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input request,
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output response
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);
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endinterface
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module CacheWithInterface(
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input logic [7:0] dataIn,
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output logic [7:0] dataOut,
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input logic clock, clear
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);
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logic [7:0] myRequest;
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logic [7:0] myResponse;
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CacheSetInterface dataInterface(
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.request(myRequest),
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.response(myResponse)
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);
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CacheSetWrapper set(
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.data(dataInterface.CacheSet),
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.clock,
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.clear
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);
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assign myRequest = dataIn;
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assign dataOut = myResponse;
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endmodule
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// to test binding a modport to another modport
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module CacheSetWrapper (
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CacheSetInterface.CacheSet data,
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input logic clock, clear
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);
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CacheSet set(data, clock, clear);
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endmodule
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module CacheSet (
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CacheSetInterface.CacheSet data,
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input logic clock, clear
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);
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always_ff @(posedge clock)
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if(clear)
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data.response <= 8'h0;
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else
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data.response <= ~data.request;
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endmodule
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