mirror of https://github.com/zachjs/sv2v.git
25 lines
524 B
Verilog
25 lines
524 B
Verilog
`default_nettype none
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module top;
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reg [1:0] select;
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// This is actually a 3x4-bit array, but must be flattened for Verilog
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wire [11:0] data;
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Example dut(
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.select(select),
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.data(data)
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);
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reg [2:0] i; // This needs to be wider than select
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initial begin
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$monitor($time, " %d = {%h}", select, data);
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select = 2'd0;
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for(i = 0; i <= 2'd3; i = i + 3'd1) begin
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#10 select = i; // Drop upper bits
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end
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#10 $finish;
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end
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endmodule
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