mirror of https://github.com/zachjs/sv2v.git
30 lines
709 B
Verilog
30 lines
709 B
Verilog
`default_nettype none
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module top;
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wire [5:0] index;
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wire [3:0] offset;
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wire [103:0] flatRequest;
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reg [10:0] dataIn;
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CacheHelper dut(
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.index(index),
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.offset(offset),
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.flatRequest(flatRequest)
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);
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assign {index, offset} = dataIn[9:0];
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initial begin
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$monitor($time, " %h %h = %h", index, offset, flatRequest);
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for (dataIn = 11'h0; dataIn <= 10'h3ff; dataIn = dataIn + 11'h1) begin
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#10;
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if (94'h277bad0badf00d0000000080 != flatRequest[93:0])
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$error("Bad fixed values");
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if (dataIn[9:0] != flatRequest[103:94])
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$error("Bad index/offset");
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end
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end
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endmodule
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