mirror of https://github.com/zachjs/sv2v.git
61 lines
2.0 KiB
Verilog
61 lines
2.0 KiB
Verilog
`default_nettype none
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`define CACHE_SETS 8
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`define CACHE_BLOCK_SIZE 'd16
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`define WORD_POISON 32'hBADF00D
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`define CACHE_PHYSICAL_TAG_POISON 22'h277BAD
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// typedef logic [5:0] CacheIndex_t;
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// typedef logic [3:0] CacheBlockOffset_t;
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// typedef logic [19:0] CacheVirtualTag_t;
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// typedef logic [21:0] CachePhysicalTag_t;
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// typedef logic [$clog2(`CACHE_SETS)-1:0] CacheSetNumber_t;
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`define CACHE_REQUEST_WIDTH 104
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// typedef struct packed {
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// CacheIndex_t index ;
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// CacheBlockOffset_t blockOffset;
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// // This field is only valid if requestType is a write
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// CachePhysicalTag_t tag ;
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// Word_t writeData ;
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// CacheRequestType_t requestType;
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// logic isValid ;
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// logic [3:0] writeEnable;
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// // The user must ensure that this set is safe to write to using the memory
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// // locking system.
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// CacheSetNumber_t writeSet;
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// } CacheRequest_t;
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module CacheHelper (
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input wire [5:0] index,
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input wire [3:0] offset,
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output wire [`CACHE_REQUEST_WIDTH-1:0] flatRequest
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);
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// CacheRequestType_t
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parameter CACHE_READ = 32'd0;
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parameter CACHE_WRITE = 32'd1;
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parameter CACHE_DRAM_FILL = 32'd2;
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function [`CACHE_REQUEST_WIDTH-1:0] readRequestManual(input [5:0] index, input [3:0] offset);
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begin
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readRequestManual[2:0] = 4'b0; // writeSet: 32-bit literal in SV truncated to 4 bits in Verilog
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readRequestManual[6:3] = 4'b0; // writeEnable
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readRequestManual[7] = 1'b1; // isValid
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readRequestManual[39:8] = CACHE_READ; // requestType
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readRequestManual[71:40] = `WORD_POISON; // writeData
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readRequestManual[93:72] = `CACHE_PHYSICAL_TAG_POISON; // tag
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readRequestManual[97:94] = offset; // blockOffset
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readRequestManual[103:98] = index; // index
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end
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endfunction
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wire [`CACHE_REQUEST_WIDTH-1:0] request;
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assign request = readRequestManual(index, offset);
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assign flatRequest = request;
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endmodule |