mirror of https://github.com/zachjs/sv2v.git
66 lines
2.0 KiB
Systemverilog
66 lines
2.0 KiB
Systemverilog
`default_nettype none
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`define CACHE_SETS 8
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`define CACHE_BLOCK_SIZE 'd16
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`define WORD_POISON 32'hBADF00D
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`define CACHE_PHYSICAL_TAG_POISON 22'h277BAD
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typedef logic [5:0] CacheIndex_t;
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typedef logic [3:0] CacheBlockOffset_t;
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typedef logic [19:0] CacheVirtualTag_t;
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typedef logic [21:0] CachePhysicalTag_t;
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typedef logic [$clog2(`CACHE_SETS)-1:0] CacheSetNumber_t;
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typedef logic [31:0] Word_t;
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typedef enum {CACHE_READ, CACHE_WRITE, CACHE_DRAM_FILL} CacheRequestType_t;
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`define CACHE_REQUEST_WIDTH 104
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typedef struct packed {
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CacheIndex_t index ;
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CacheBlockOffset_t blockOffset;
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// This field is only valid if requestType is a write
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CachePhysicalTag_t tag ;
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Word_t writeData ;
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CacheRequestType_t requestType;
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logic isValid ;
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logic [3:0] writeEnable;
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// The user must ensure that this set is safe to write to using the memory
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// locking system.
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CacheSetNumber_t writeSet;
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} CacheRequest_t;
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module CacheHelper (
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input logic [5:0] index,
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input logic [3:0] offset,
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output logic [`CACHE_REQUEST_WIDTH-1:0] flatRequest
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);
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generate
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if($bits(CacheRequest_t) != `CACHE_REQUEST_WIDTH)
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BadTypeLayout foo();
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endgenerate
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function automatic CacheRequest_t readRequestManual(CacheIndex_t index, CacheBlockOffset_t offset);
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return '{
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index: index,
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blockOffset: offset,
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tag: `CACHE_PHYSICAL_TAG_POISON,
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writeData: `WORD_POISON,
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requestType: CACHE_READ,
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isValid: 1'b1,
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writeEnable: 0,
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// This is effectively 32-bits wide which is sufficient, but not technically correct. The "compiler" will truncate the bits to the width of 'writeSet'
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writeSet: '0
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};
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endfunction
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CacheRequest_t request;
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assign request = readRequestManual(index, offset);
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assign flatRequest = request;
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endmodule
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