mirror of https://github.com/zachjs/sv2v.git
83 lines
2.0 KiB
Verilog
83 lines
2.0 KiB
Verilog
`default_nettype none
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module top;
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reg [2:0] operation;
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reg [31:0] left, right;
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wire [31:0] result;
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ALU dut(
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.operation(operation),
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.left(left),
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.right(right),
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.result(result)
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);
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initial begin
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$monitor($time, " %h %d %h = %h", left, operation, right, result);
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operation = 3'd0;
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left = 32'h0;
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right = 32'h0;
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#10;
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left = 32'h80000000;
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right = 32'd16;
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#10;
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operation = 3'd1;
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#10;
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left = 32'h7fff0003;
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right = 32'd1;
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#10;
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right = 32'd0;
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#10;
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right = 32'd8;
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#10;
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operation = 3'd2;
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left = 32'hffffffff;
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right = 32'h10;
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#10;
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left = 32'h1;
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right = 32'h10;
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#10;
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left = 32'h10;
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right = 32'hffffffff;
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#10;
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operation = 3'd3;
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left = 32'h80000000;
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right = 32'h7fffffff;
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#10;
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left = 32'hff;
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right = 32'h80000000;
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#10;
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operation = 3'd2;
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left = 32'd10;
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right = 32'd20;
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#10;
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left = 32'd20;
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right = 32'd10;
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#10;
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left = 32'hffffffff; // -1
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right = 32'hfffff000;
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#10;
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left = 32'hfffff000;
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right = 32'hffffffff;
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#10;
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left = 32'hfffff000;
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right = 32'h10;
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#10;
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left = 32'h10;
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right = 32'hfffff000;
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#10;
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// operation = 3'd1;
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// // for(left = 32'b0; left < 32'hffffffff; left = left + 32'b1)
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// // for(right = 32'b0; right <= 32'd31; right = right + 32'b1)
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// // #10 if(result != dut.result2) $error("Bad match: %h %h", result, dut.result2);
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// // #10;
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// left = 32'hffffffff;
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// for(right = 32'b0; right <= 32'd31; right = right + 32'd1)
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// #10 if(result != dut.result2) $error("Bad match: %h %h", result, dut.result2);
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// #10;
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$finish;
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end
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endmodule
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