mirror of https://github.com/zachjs/sv2v.git
214 lines
6.1 KiB
Bash
214 lines
6.1 KiB
Bash
#!/bin/bash
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SCRIPT_DIR=`dirname "${BASH_SOURCE[0]}"`
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SV2V="$SCRIPT_DIR/../../bin/sv2v +RTS -N1 -RTS"
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# USAGE: simulate <vcd-file> <log-file> <file> [<file> ...]
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simulate() {
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# arguments
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sim_vcd=$1
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sim_log=$2
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shift 2
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# compile the files
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sim_vcd_tmp=$SHUNIT_TMPDIR/simvcdtmp
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sim_prog=$SHUNIT_TMPDIR/simprog.exe
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iv_output=`iverilog \
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-Wall \
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-Wno-portbind \
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-o $sim_prog \
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-g2005 \
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-gstrict-expr-width \
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-DTEST_VCD=\"$sim_vcd_tmp\" \
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"$@" \
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$SCRIPT_DIR/tb_dumper.v \
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2>&1`
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if [ $? -ne 0 ]; then
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fail "iverilog on $1 failed:\n$iv_output"
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return
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elif [ "$EXPECT_IVERILOG_WARNINGS" != "0" ]; then
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assertNull "iverilog on $1 emitted warnings:\n$iv_output" "$iv_output"
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else
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assertNotNull "iverilog on $1 did not emit any warnings" "$iv_output"
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fi
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# run the simulation
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$sim_prog -no-date > $sim_log
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assertTrue "simulating $1 failed" $?
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# remove parameters from the VCD if present
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if grep -E "var parameter| _sv2v_0 " $sim_vcd_tmp > /dev/null; then
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$SCRIPT_DIR/clean_vcd.py < $sim_vcd_tmp > $sim_vcd
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elif [ $sim_vcd != "/dev/null" ]; then
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mv -f $sim_vcd_tmp $sim_vcd
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fi
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}
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assertConverts() {
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ac_file=$1
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ac_tmpa=$SHUNIT_TMPDIR/ac-conv-tmpa.v
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convert "1st conversion of $ac_file" $ac_tmpa $ac_file
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# check for un/expected output in the converted result
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ac_pats=$ac_file.pat
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if [ -f $ac_pats ]; then
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while read line; do
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rule=${line:0:6}
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pattern=${line:7}
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grep -F "$pattern" < $ac_tmpa > /dev/null
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matches=$?
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if [ $rule == "affirm" ]; then
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assertTrue "conversion of $ac_file does not contain $pattern" $matches
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elif [ $rule == "reject" ]; then
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assertFalse "conversion of $ac_file contains $pattern" $matches
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else
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fail "unknown rule type: '$rule'"
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fi
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done < $ac_pats
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fi
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ac_tmpb=$SHUNIT_TMPDIR/ac-conv-tmpb.v
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convert "2nd conversion of $ac_file" $ac_tmpb $ac_tmpa
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diff $ac_tmpa $ac_tmpb > /dev/null
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assertTrue "conversion of $ac_file not stable after the first iteration" $?
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ac_tmpc=$SHUNIT_TMPDIR/ac-conv-tmpc.v
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convert "pass through of $ac_file" $ac_tmpc --pass-through $ac_file
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ac_tmpd=$SHUNIT_TMPDIR/ac-conv-tmpd.v
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convert "conversion of pass through of $ac_file" $ac_tmpd $ac_tmpc
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# remove source locations when checking the --pass-through invariant
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removeSourceLocation $ac_file $ac_tmpa
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removeSourceLocation $ac_tmpc $ac_tmpd
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diff $ac_tmpa $ac_tmpd > /dev/null
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assertTrue "pass through then conversion differs for $ac_file" $?
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# using sed to remove quoted strings
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filtered=`sed -E 's/"([^"]|\")+"//g' $ac_tmpa`
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# check for various things iverilog accepts which we don't want to output
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prefix="conversion of $ac_file still contains"
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assertNotMatch "$prefix dimension queries" "$filtered" \
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'\$bits|\$dimensions|\$unpacked_dimensions|\$left|\$right|\$low|\$high|\$increment|\$size'
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assertNotMatch "$prefix SystemVerilog types" "$filtered" \
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'[[:space:]](int|bit|logic|byte|struct|enum|longint|shortint)[[:space:]]'
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assertNotMatch "$prefix unsigned keyword" "$filtered" \
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'[^\$a-zA-Z_]unsigned'
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}
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extractFlag() {
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raw_line=`grep -m1 "^// $1: " $2`
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to_drop=$((${#1}+5))
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flag="${raw_line:to_drop}"
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}
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assertMatch() {
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if [[ ! "$2" =~ $3 ]]; then
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fail "$1 doesn't match\nexpected: $3\nactual: $2"
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fi
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}
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assertNotMatch() {
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if [[ "$2" =~ $3 ]]; then
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fail "$1"
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fi
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}
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# convert SystemVerilog source file(s)
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convert() {
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description=$1
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out_file=$2
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shift 2
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$SV2V "$@" 2> $SHUNIT_TMPDIR/stderr > $out_file
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assertTrue "$description failed" $?
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if [ -s $SHUNIT_TMPDIR/stderr ]; then
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fail "$description emitted warnings:"
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cat $SHUNIT_TMPDIR/stderr
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fi
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}
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simpleTest() {
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sv=$1
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ve=$2
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tb=$3
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assertConverts $sv
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# some tests use inputs compatible with iverilog directly and so omit the
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# reference manually converted file
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if [ ! -f $ve ]; then
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ve=$sv
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else
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assertConverts $ve
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fi
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# some tests don't have a separate testbench, instead having the top-level
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# module defined in both of the input files
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if [ ! -f $tb ]; then
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tb=$SCRIPT_DIR/empty.v
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else
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assertConverts $tb
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fi
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cs=$SHUNIT_TMPDIR/cs.v
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convert "standard conversion" $cs $sv
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cv=$SHUNIT_TMPDIR/cv.v
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convert "verbose conversion" $cv $sv -v
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simulateAndCompare $ve $cs $cv $tb
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}
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simulateAndCompare() {
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ve=$1 # reference verilog
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cs=$2 # converted succinct
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cv=$3 # converted verbose
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tb=$4 # testbench
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ref_vcd=$SHUNIT_TMPDIR/ref.vcd
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cvs_vcd=$SHUNIT_TMPDIR/cvs.vcd
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cvv_vcd=$SHUNIT_TMPDIR/cvv.vcd
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ref_log=$SHUNIT_TMPDIR/ref.log
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cvs_log=$SHUNIT_TMPDIR/cvs.log
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cvv_log=$SHUNIT_TMPDIR/cvv.log
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# simulate the three files
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simulate $ref_vcd $ref_log $ve $tb
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simulate $cvs_vcd $cvs_log $cs $tb
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simulate $cvv_vcd $cvv_log $cv $tb
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# clean log files by source locations
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removeSourceLocation $ve $ref_log
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removeSourceLocation $cs $cvs_log
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removeSourceLocation $cv $cvv_log
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# compare reference verilog to converted succinct
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output=`diff $ref_vcd $cvs_vcd`
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assertTrue "VE/CS VCDs are different:\n$output" $?
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output=`diff $ref_log $cvs_log`
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assertTrue "VE/CS simulation outputs differ:\n$output" $?
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# compare converted verbose to converted succinct
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output=`diff $cvv_vcd $cvs_vcd`
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assertTrue "CV/CS VCDs are different:\n$output" $?
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output=`diff $cvv_log $cvs_log`
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assertTrue "CV/CS simulation outputs differ:\n$output" $?
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rm -f $ref_vcd $cvs_vcd $cvv_vcd $ref_log $cvs_log $cvv_log
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}
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runTest() {
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test=$1
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simpleTest "${test}.sv" "${test}.v" "${test}_tb.v"
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}
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runAndCapture() {
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$SV2V "$@" > "$SHUNIT_TMPDIR/stdout" 2> "$SHUNIT_TMPDIR/stderr"
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result=$?
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stdout=`cat $SHUNIT_TMPDIR/stdout`
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stderr=`cat $SHUNIT_TMPDIR/stderr`
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}
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removeSourceLocation() {
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sed -i.bak -E 's#'$1':[0-9]+(:[0-9]+)?#<removed_source_location>#g' $2
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}
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