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12 lines
245 B
Systemverilog
12 lines
245 B
Systemverilog
module top;
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function automatic integer f;
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input integer x;
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output integer y;
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f = x * 3;
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y = x * 5;
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endfunction
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logic signed [31:0] x, y;
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initial x = f(-1, y);
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initial $display(x, y);
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endmodule
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