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Zachary Snow
2885e21cdd
- preproc reads identifiers unconditionally - drop leading whitespace for default macro args - very minor preproc cleanup
24 lines
447 B
Systemverilog
24 lines
447 B
Systemverilog
`define FELSE `else
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`define MACRO_A(flag, check1 = ifdef, check2 = else) \
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initial $display( \
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`check1 flag \
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`"flag is check1'd`" \
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`check2 \
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`"flag is not check1'd`" \
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`endif \
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);
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`define A
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module top;
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`MACRO_A(A)
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`MACRO_A(B)
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`MACRO_A(A, ifndef)
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`MACRO_A(B, ifndef)
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`MACRO_A(A, ifdef, FELSE)
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`MACRO_A(B, ifdef, FELSE)
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`MACRO_A(A, ifndef, FELSE)
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`MACRO_A(B, ifndef, FELSE)
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endmodule
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