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9 lines
206 B
Verilog
9 lines
206 B
Verilog
module top;
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initial begin
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$display("line.sv", `__LINE__);
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$display("fake.v", 102);
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$display("via include: ", "./line.vh", 1);
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$display("line.vh", 201);
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end
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endmodule
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