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Zachary Snow
0a7b0250e7
- swap 1364-2001 and 1364-2001-noconfig - fix existing begin_keywords test - add keyword test suite for all keywords
27 lines
431 B
Verilog
27 lines
431 B
Verilog
module top;
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task foo;
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integer x;
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begin
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x = 2;
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$display(x * x);
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end
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endtask
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task bar;
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integer y;
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begin
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y = 3;
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$display(y * y);
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end
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endtask
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task baz;
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integer w;
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begin
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w = 3;
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$display(w ** w);
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end
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endtask
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initial foo;
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initial bar;
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initial baz;
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endmodule
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