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9 lines
217 B
Systemverilog
9 lines
217 B
Systemverilog
// pattern: illegal access to range \[0\+:1\] of s\.x, which has type logic
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// location: struct_logic_part_select.sv:7:13
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module top;
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struct packed {
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logic x;
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} s;
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initial s.x[0+:1] = 1;
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endmodule
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