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Zachary Snow
95c2bc996c
Specifically, support has been added for non-ANSI style port declarations where the port declaration is separate from the corresponding net or variable declaration.
5 lines
115 B
Systemverilog
5 lines
115 B
Systemverilog
// pattern: declared ports w, z are not in the port list of top
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module top(x, y);
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output w, x, y, z;
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endmodule
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