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Zachary Snow
95c2bc996c
Specifically, support has been added for non-ANSI style port declarations where the port declaration is separate from the corresponding net or variable declaration.
6 lines
177 B
Systemverilog
6 lines
177 B
Systemverilog
// pattern: declarations `output a = 1` and `logic a` are incompatible due to invalid initialization at port declaration
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module top(a);
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output a = 1;
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logic a;
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endmodule
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