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https://github.com/zachjs/sv2v.git
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Zachary Snow
5fd21ebfb0
- support for additional assignment statements in loop initializations - greatly improved error messaging in these contexts - decl parser takes in the ending token; significant related refactoring - pass through elaboration system tasks - removed non-blocking assignment operator precedence hack - preliminary nosim test suite for features unsupported by iverilog
5 lines
142 B
Systemverilog
5 lines
142 B
Systemverilog
// pattern: instantiation_missing_ports\.sv:3:14: Parse error: expected port connections before ','
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module top;
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example a, c();
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endmodule
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