Files
sv2v/test/error/for_loop_init_stray.sv
Zachary Snow 5fd21ebfb0 improved parsing in declaration contexts
- support for additional assignment statements in loop initializations
- greatly improved error messaging in these contexts
- decl parser takes in the ending token; significant related refactoring
- pass through elaboration system tasks
- removed non-blocking assignment operator precedence hack
- preliminary nosim test suite for features unsupported by iverilog
2021-07-05 18:00:12 -04:00

5 lines
133 B
Systemverilog

// pattern: for_loop_init_stray\.sv:3:22: Parse error: expected ',' or ';'
module top;
initial for (a++ b++; 1; a++) ;
endmodule