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https://github.com/zachjs/sv2v.git
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Zachary Snow
5fd21ebfb0
- support for additional assignment statements in loop initializations - greatly improved error messaging in these contexts - decl parser takes in the ending token; significant related refactoring - pass through elaboration system tasks - removed non-blocking assignment operator precedence hack - preliminary nosim test suite for features unsupported by iverilog
6 lines
183 B
Systemverilog
6 lines
183 B
Systemverilog
// pattern: for_loop_init_delay\.sv:4:20: Parse error: unexpected timing modifier in for loop initialization
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module top;
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integer x;
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initial for (x = #1 1; 1; x++) ;
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endmodule
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