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Zachary Snow
6c4ee8f4bc
These are now kept while still supporting optional trailing commas and without introducing pass-through inconsistencies.
10 lines
181 B
Systemverilog
10 lines
181 B
Systemverilog
// pattern: illegal mix of ordered and named port connections
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module example(
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input a, b, c
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);
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endmodule
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module top;
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wire a, b, c;
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example e(.a(1), .b(2), ,);
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endmodule
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