mirror of
https://github.com/zachjs/sv2v.git
synced 2026-08-30 01:18:10 +02:00
Zachary Snow
306d71334b
- use iverilog's -gstrict-expr-width throughout test suite - add warnings for excess bits or padding zeroes in number literals - add new --oversized-numbers parameter to retain support for unsized numbers wider than 32 bits - localized use of oversized numbers to new truncate test suite which verifies the behavior of both modes, and compares against the known behavior of iverilog
11 lines
243 B
Verilog
11 lines
243 B
Verilog
module top;
|
|
initial begin
|
|
$display($signed(1'b1));
|
|
$display($unsigned(1'sb1));
|
|
$display($signed(1));
|
|
$display($unsigned(1));
|
|
$display($signed(-1));
|
|
$display($unsigned(-1));
|
|
end
|
|
endmodule
|