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16 lines
354 B
Verilog
16 lines
354 B
Verilog
module Example(inp, out);
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parameter ENABLED = 1;
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localparam [0:0] DEFAULT = 1'b0;
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input wire inp;
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output reg out;
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generate
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if (ENABLED) begin
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reg start;
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always @(inp, start) out = inp;
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initial start = 0;
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end
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else
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initial out = DEFAULT;
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endgenerate
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endmodule
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