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11 lines
230 B
Systemverilog
11 lines
230 B
Systemverilog
module Example(inp, out);
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parameter ENABLED = 1;
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localparam [0:0] DEFAULT = 1'b0;
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input logic inp;
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output logic out;
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if (ENABLED)
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always_comb out = inp;
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else
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assign out = DEFAULT;
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endmodule
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