mirror of
https://github.com/zachjs/sv2v.git
synced 2026-08-30 01:18:10 +02:00
Zachary Snow
5fd21ebfb0
- support for additional assignment statements in loop initializations - greatly improved error messaging in these contexts - decl parser takes in the ending token; significant related refactoring - pass through elaboration system tasks - removed non-blocking assignment operator precedence hack - preliminary nosim test suite for features unsupported by iverilog
21 lines
393 B
Verilog
21 lines
393 B
Verilog
module top;
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`define LOOP(ID, START) \
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x = 0; \
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for (x = START; x < 3; x = x + 1) \
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$display(`"ID x = %0d`", x);
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initial begin : blk
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integer x;
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`LOOP(A, 1)
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`LOOP(B, 1)
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`LOOP(C, 1)
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`LOOP(D, 0)
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`LOOP(E, 0)
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`LOOP(F, 1)
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`LOOP(G, 1)
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`LOOP(H, -1)
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`LOOP(I, -1)
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`LOOP(J, -1)
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end
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endmodule
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