mirror of
https://github.com/zachjs/sv2v.git
synced 2026-08-30 01:18:10 +02:00
Zachary Snow
5fd21ebfb0
- support for additional assignment statements in loop initializations - greatly improved error messaging in these contexts - decl parser takes in the ending token; significant related refactoring - pass through elaboration system tasks - removed non-blocking assignment operator precedence hack - preliminary nosim test suite for features unsupported by iverilog
59 lines
1.3 KiB
Systemverilog
59 lines
1.3 KiB
Systemverilog
module top;
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initial begin
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integer x, y;
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x = 0;
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y = 3;
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for (x += 1; x < y; x++)
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$display("A x = %0d", x);
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end
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initial begin
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integer x, y;
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x = 0;
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for (x += 1, y = 3; x < y; x++)
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$display("B x = %0d", x);
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end
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initial begin
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integer x, y;
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x = 0;
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for (y = 3, x += 1; x < y; x++)
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$display("C x = %0d", x);
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end
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initial
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for (integer x = 0, y = 3; x < y; x++)
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$display("D x = %0d", x);
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initial
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for (integer x = 0, byte y = 3; x < y; x++)
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$display("E x = %0d", x);
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initial begin
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integer x, y;
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x = 0;
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for (x++, y = 3; x < y; x++)
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$display("F x = %0d", x);
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end
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initial begin
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integer x, y;
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x = 0;
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for (y = 3, x++; x < y; x++)
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$display("G x = %0d", x);
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end
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initial begin
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integer x, y;
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x = 0;
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for (--x, y = 3; x < y; x++)
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$display("H x = %0d", x);
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end
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initial begin
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integer x, y;
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x = 0;
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for (y = 3, --x; x < y; x++)
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$display("I x = %0d", x);
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end
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initial begin
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integer x, y;
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x = 0;
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y = 2;
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for (--y, ++y, y++, ++x, --x, --x; x < y; x++)
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$display("J x = %0d", x);
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end
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endmodule
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