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Zachary Snow
bfd0cee0dc
- convert loops with no or many incrementations - restrict AST node to only contain traditional initializations - parser elaborates for loop decls into a synthetic block - decl list codegen is now specific to parameter decl lists - update jump conversion special cases for new representation - first experiments with bimapM
15 lines
370 B
Verilog
15 lines
370 B
Verilog
module top;
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initial begin : blk1
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integer x, y, z;
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y = 10;
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z = 101;
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for (x = 0; x < y; {x, y, z} = {x + 32'd1, y - 32'd2, z >> 1})
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$display("x = %0d, y = %0d, z = %0d", x, y, z);
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end
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initial begin : blk2
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integer x;
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for (x = 0; x < 3; x = x + 1)
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$display("x = %0d", x);
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end
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endmodule
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