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Zachary Snow
bfd0cee0dc
- convert loops with no or many incrementations - restrict AST node to only contain traditional initializations - parser elaborates for loop decls into a synthetic block - decl list codegen is now specific to parameter decl lists - update jump conversion special cases for new representation - first experiments with bimapM
11 lines
302 B
Systemverilog
11 lines
302 B
Systemverilog
module top;
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initial
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for (integer x = 0, y = x + 10, z = y * 10 + 1; x < y; x += 1, y -= 2, z >>= 1)
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$display("x = %0d, y = %0d, z = %0d", x, y, z);
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initial
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for (integer x = 0; x < 3; ) begin
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$display("x = %0d", x);
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++x;
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end
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endmodule
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