mirror of
https://github.com/zachjs/sv2v.git
synced 2026-09-03 08:33:46 +02:00
11 lines
197 B
Verilog
11 lines
197 B
Verilog
module mod(input clk);
|
|
reg x, z;
|
|
wire y;
|
|
initial begin
|
|
$display(x, y, z);
|
|
z = 1;
|
|
x = @(posedge y or posedge clk) z;
|
|
$display(x, y, z);
|
|
end
|
|
endmodule
|