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19 lines
359 B
Verilog
19 lines
359 B
Verilog
module top;
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reg [3:0] idx;
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reg [14:0] data;
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mod m(idx, data);
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initial begin
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#1 data = 0;
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#1 idx = 0;
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#1 data[0] = 1;
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#1 data[4] = 1;
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#1 data[5] = 1;
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#1 data[3] = 1;
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#1 data[8] = 1;
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#1 idx = 0;
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#1 idx = 1;
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#1 data[0] = 0;
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#1 data[0] = 1;
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end
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endmodule
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