mirror of
https://github.com/zachjs/sv2v.git
synced 2026-08-30 01:18:10 +02:00
11 lines
172 B
Verilog
11 lines
172 B
Verilog
module test(a, b, en);
|
|
output reg a;
|
|
input wire b;
|
|
input wire en;
|
|
always @(*) begin
|
|
if (en) begin
|
|
a <= b;
|
|
end
|
|
end
|
|
endmodule
|