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13 lines
289 B
Systemverilog
13 lines
289 B
Systemverilog
reg never;
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`define TEST(sense, num) \
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reg x``num, y``num, z``num; \
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function automatic t``num; \
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input inp; \
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t``num = x``num + x``num; \
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endfunction \
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always``sense begin \
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y``num = 0; \
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z``num = t``num(0); \
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if (never) ; \
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end
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