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18 lines
312 B
Systemverilog
18 lines
312 B
Systemverilog
module top;
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`define TEST(sense) always sense $display(`"sense %b`", x);
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reg x, y;
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`TEST(@*)
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`TEST(@ *)
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`TEST(@x)
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`TEST(@y)
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`TEST(@ ( * ))
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`TEST(@ ( *))
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`TEST(@ (* ))
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`TEST(@ (*))
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`TEST(@( * ))
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`TEST(@( *))
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`TEST(@(* ))
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`TEST(@(*))
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initial x = 1;
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endmodule
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