mirror of
https://github.com/zachjs/sv2v.git
synced 2026-08-31 01:34:16 +02:00
619bde4be1
Co-authored-by: qcorradi <[email protected]> Co-authored-by: Zachary Snow <[email protected]>
5 lines
118 B
Systemverilog
5 lines
118 B
Systemverilog
module top;
|
|
wire a, b, c, d, e;
|
|
assign a = b ? (* ternary *) ~^ (* unary *) c : d & (* binary *) e;
|
|
endmodule
|