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Zachary Snow
2a2d819baa
- assertions, gen case, and inout - simplify block codegen - remove blank lines in tasks with no inputs
10 lines
130 B
Systemverilog
10 lines
130 B
Systemverilog
module top;
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task t;
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input x;
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begin : y
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reg z;
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end
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endtask
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initial t(0);
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endmodule
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