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sv2v
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112 Commits 1 Branch 14 Tags 3.4 MiB
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112 Commits

Author SHA1 Message Date
Zachary Snow 39ee22574f support for multi-line defines 2019-02-11 01:51:09 -05:00
Zachary Snow cb42f37bb2 removed support for inital and delays 2019-02-10 18:56:01 -05:00
Zachary Snow 767b05cd06 arguably cleaner Show output for AST modules 2019-02-10 17:59:41 -05:00
Zachary Snow 14ba5dae6d support for reduction ops, non-named/non-identifier module instantiation arguments, always @* 2019-02-10 17:47:11 -05:00
Zachary Snow 5b336439fb cleanup of port decl parsing 2019-02-09 18:35:15 -05:00
Zachary Snow ebd7ae67b1 hacky, preliminary support for port declarations in module header 2019-02-09 17:35:31 -05:00
Zachary Snow 0f2638075b updated build procedure 2019-02-08 16:51:32 -05:00
Zachary Snow fb8f088bad updated LICENSE to reflect fork 2019-02-08 16:51:20 -05:00
Zachary Snow 8bd58e961f Basic build setup! 2019-02-08 01:09:33 -05:00
Zachary Snow b46009af53 Refactor project setup for our purposes 2019-02-08 00:19:39 -05:00
Zachary Snow bfafea5dd8 Fix compiliation; trailing whitespace; added .gitignore 2019-02-07 23:58:34 -05:00
Zachary Snow 363ca80af2 Initial commit: fork of https://github.com/tomahawkins/verilog 2019-02-07 23:49:12 -05:00