7 Commits

Author	SHA1	Message	Date
Zachary Snow	a432d75939	additional SystemVerilog language support ... - unique0 and priority - uniqueness on if statements - preliminary discard-only parsing of assertions - parameters with alias typenames	2019-03-30 00:47:42 -04:00
Zachary Snow	d578aee5d9	conflate the preprocessor and lexer ... This should make it much easier to add support for ``, `", macros with arguments, etc., in the future.	2019-03-29 05:33:17 -04:00
Zachary Snow	e69895af54	initial setup for combining pre-processor and lexer	2019-03-29 01:10:46 -04:00
Zachary Snow	cecd141e57	revamped support system with most SystemVerilog types and signed types	2019-03-22 17:45:31 -04:00
Zachary Snow	acfbdb07f8	completely rewrote preprocessor; more extensive directive support (include, timescale)	2019-03-18 05:00:23 -04:00
Zachary Snow	460c0ee497	broader operator support; other parser cleanup	2019-03-04 18:25:14 -05:00
Zachary Snow	7bc81ef67b	directory re-org; streamline build setup	2019-02-28 13:52:31 -05:00