7 Commits

Author	SHA1	Message	Date
Zachary Snow	33dc4b3f88	conversions are applied per-file ... - NestTF refactored to cover all package items - fixed issue where type traverse skipped typedefs	2019-04-23 18:51:39 -04:00
Zachary Snow	c8894cebde	random documentation and cleanup	2019-04-23 00:23:32 -04:00
Zachary Snow	cecd141e57	revamped support system with most SystemVerilog types and signed types	2019-03-22 17:45:31 -04:00
Zachary Snow	d7f641b850	pivoted to general Verilog-2005 targeting	2019-03-08 11:02:40 -05:00
Zachary Snow	9f0857d68e	some fixes for 'VTR' targetted conversions	2019-03-07 20:03:35 -05:00
Zachary Snow	0f4a60be1d	functions and typedefs can now appear at the top level	2019-03-07 13:19:31 -05:00
Zachary Snow	4c49bd1138	function return type logic to implicit conversion	2019-03-06 14:36:16 -05:00